The tremendous achievements in the chip technology allow to produce chips with hundreds million gates. At the same time, the design technology of such circuits only slightly improved in the last ten years, especially at the highest system level. The traditional digital system design flow contains the manual creation of system description at the Register Transfer Level (hereafter RTL) with Verilog or VHDL code. The only possibility to reduce a gap between future technological capability and the lagging designer productivity is to raise the design from the current RTL to the algorithmic or behavior level i.e. to High Level Synthesis (HLS). For that it is necessary to solve several problems: 1. Develop models for describing systems at a high level; 2. Develop tools based on these models; 3. Develop a design methodology based on these models and tools. My book is about HLS. However, the models and methods presented in this book are fundamentally different from those used in the known industrial and academic instruments. In this book I used Algorithmic State Machines (hereafter ASMs) at all stages of high level and RTL designs. You will be very surprised, when you understand that it is possible to design very complex digital systems, beginning from ASMs. Most ideas from this book were realized in HLS tool Synthagate – the product of Synthezza. I used it to construct all examples in this book. Synthagate is a tool for design of Control and Data Path Intensive Systems with very complex Control Units containing numerous inputs and outputs. Synthagate performs full automatic synthesis of digital systems from behavior specification to description in HDL at RTL, and allows the user to quickly implement, check and estimate multiple design versions, to find an optimized solution for the design problems, to produce automatically the design documentation and to simplify the digital system verification problems. The main steps of HLS and RTL design: Functional Specifications. To design the behavior description of a digital system the designer should not define each port or signal. Synthagate automatically creates the functional specification. Behavior description of the design system. With Functional ASM and functional specification as an input, Synthagate automatically constructs the behavior (High Level) description of the whole design system in VHDL or in System C. Data path design. In Data path design Synthagate uses external specification in XML constructed automatically. Automatic generation of components. Synthagate automatically generates VHDL codes for components of Data Path. If a designer would like to use some predesigned IP cores, he must put their RTL codes in the special folder before the design at High level. Generation VHDL code for Data Path. At the last step of Data Path design Synthagate automatically instantiates components in the Data Path. Control Unit design. Synthagate automatically creates the RTL code of Control unit. Top design. At the last stage, Synthagate automatically creates the code for the top level by instantiating Control Unit and Data Path into the top of the project. This book can be useful for hardware designers and hardware engineers, undergraduate and graduate students of Computer engineering and Electrical engineering departments and their teachers. I gave many examples in the main part and in the Case study sections. Whole designs of these examples and many others you will find on the site of Synthezza from the links of this book. You can look at this book as the second part of my previous book "Finite State Machines and Algorithmic State Machines", published recently. Why did I decide to publish these two books as eBooks? I wanted that these books be affordable even for students and novice engineers. So, I’ve decided that cost of eBooks wouldn’t be over 10 dollars—around the same amount that a student spends on two coffees and a small pastry for his girlfriend at Starbucks. Read more
